搜索资源列表
UART
- 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
RS485EN
- RS485的双向通信处，正在为此头疼的同学们可要注意了，这个可以解决你们双向通信过程中的很多问题哦-Two-way RS485 communications, the headache is to this end they' ll pay attention to the students, this two-way communication you can solve many problems in the course of oh
PCMverilog
- 实现了数字通信系统中PCM编码，用Verilog硬件描述语言编程在FPGA上实现的。-Achieved in the PCM coded digital communication system, using Verilog hardware descr iption language programming implemented on the FPGA.
QAM16_Souce_code
- QAM 16 源代码，用于无线通信中或者广播中的调制。-QAM 16 source code, used in wireless communication or broadcasting.
lcom
- 很经典的单片机程序，可以实现单片机与FPGA的通信-Is the classic single-chip process can be achieved with single-chip FPGA communications
Serial
- FPGA与PC串口通信的Verilog HDL 程序-FPGA and the PC serial communication procedures Verilog HDL
06_fpga
- PAX270平台下，与FPGA通信的原代码-PAX270 platform with FPGA communications original code
Uartmodule
- 实现FPGA与PC机的串口通信功能，实现数据的收发。-FPGA with the realization of PC-serial communication functions to send and receive data.
VHDL_DMF
- Vhdl实现扩频通信匹配滤波器，书上打下来的,打了好久.-VHDL realization of spread spectrum communication matched filter, books, playing down, playing for a long time.
FPGADDS
- 基于FPGA的DDS信号发生器的简单实现。DDS（直接数字合成）是近年来迅速发展起来的一种新的频率合成方法。这种方法简单可靠、控制方便，且具有很高的频率分辨率和转换速度，非常适合快速跳频通信的要求。 -FPGA-based signal generator DDS simple to achieve. DDS (direct digital synthesis) is a rapidly in recent years developed a new method of frequency sy
cy7c63743
- CY7C68013单片机通信测试:数据从控制面板传入EP1IN端点，然后送入IOA端口，然后程序读取IOA端口，送入EP1IN端点，在控制面板显示。-CY7C68013 Singlechip communications test: data from the control panel EP1IN incoming endpoint, and then into the IOA port, and then the procedure to read IOA port, into EP1IN
USB2.0FPGAEXAMPLES
- 用于USB20芯片CY7C68013和FPGA之间的通信-comunication between USB and FPGA
feng_rs0
- 基于FPGA的串口通信，PC给FPGA发送数据，FPGA收到数据并返回给PC-FPGA-based serial communications, PC to the FPGA to send data, FPGA Receive data and return to the PC
uart01
- 一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序-A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure
FSKmodulationanddemodulation
- FSK调制与解调，整个设计基于ALTERA公司的QuartusⅡ开发平台，并用Cyclone系列FPGA实现。所设计的调制解调器具有体积小、功耗低、集成度高、软件可移植性强、扰干扰能力强的特点,符合未来通信技术设计的方向。-FSK modulation and demodulation, the entire design is based on ALTERA' s development platform Quartus Ⅱ, and Cyclone series FPGA implem
fpga_designing_lvds_communication
- 开发 fpga LVDS的通信文档,pdf格式。应该对你的设计有帮助-fpga design lvds，pdf format, you can study thids
LVDS_DDR_List_FPGA2
- FPGA芯片与ADI公司的AD9779之间的通信，总共有四个通道，68对LVDS,采样时钟是122.88MHz-FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
UART
- UART通信协议的硬件描述语言代码，用与FPGA的总线接口开发-UART communication protocol of the hardware descr iption language code, using the bus interface with the FPGA development
canbus
- CAN通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-CAN communication protocol of the hardware descr iption language code for the FPGA bus interface controller development
Mars_EP1C6F_Interface_demo(VHDL)
- FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。-FPGA development board support VHDL code. Chips for the Mars EP1C6F. Some of the source interface. Including 7 digital tube, I2C communications.